For purposes of station tuning in radio receivers, a phase control loop ("Phase-Locked Loop," hereinafter "PLL") is frequently used, where the frequency of a controllable oscillator is divided, and the signal with the divided frequency is compared to the signal of a reference oscillator in a phase detector, whereby a tuning voltage is produced that can be supplied to the controllable oscillator. Dependent on the selected frequency of the reference oscillator, frequency division by an uneven (odd) number is often required to achieve the desired tuning pattern. In particular, a duty cycle of near 1 is required for analog processing of the frequency-divided signal, due to factors based on performance.